![]() ![]() the fact that the instruction set is non-orthogonal (32-bit fixed encoding makes the decoder simple, but creates the same load-store problem as on SPARC - hello non-existent, synthetic instructions!) the fact that this processor design is being aggressively pushed here (featured several times already) ![]() the assembler dst, src backward syntax (like intel) I understand that designing processors is fun, but I hold several things against RISC-V:
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